MicroCloud Hologram Inc. Utilizes FPGA to Accelerate Tensor Network Computing to Achieve Quantum Spin Models

SHENZHEN, China, Jan. 16, 2026 — MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the “Company”), a technology service provider, has proposed an innovative hardware-acceleration approach that converts quantum tensor network algorithms into parallel computing circuits runnable on field-programmable gate arrays (FPGA). The method achieves efficient quantum spin model simulation on classical hardware and provides a new engineered path for quantum physics research, quantum algorithm verification, and digital-twin simulation of future quantum devices.

In research of quantum many-body systems, the tensor network (TN) algorithm is an extremely efficient numerical tool. It mitigates exponential state-space growth by decomposing high-dimensional quantum states into a network of lower-dimensional tensors. Typical tensor-network forms include matrix product states (MPS), projected entangled pair states (PEPS), and multi-scale entanglement renormalization (MERA). These algorithms underpin condensed-matter physics, quantum phase transition analysis, and quantum spin model simulations.

However, increasing the precision of system characterization and introducing higher entanglement degrees of freedom causes tensor dimensions and connectivity to grow sharply, driving computational complexity from polynomial to near-exponential. For example, in a two-dimensional spin system, when the entanglement rank increases from χ = 8 to χ = 32, floating-point operations per iteration can increase by nearly two orders of magnitude; storage bandwidth and memory-access latency then become bottlenecks. This exponential growth makes it difficult for even high-end CPUs and GPUs to complete simulations in reasonable time.

To address these limits, HOLO explored algorithm reconstruction and logic mapping at the hardware level. FPGAs, with reconfigurability, fine-grained parallelism, and low latency, open new possibilities for tensor-network computation. By mapping core computational modules (tensor contraction, tensor unfolding, matrix multiply-add operations, etc.) directly into hardware logic, HOLO reduced memory-access overhead and control overhead and achieved deep-pipelined, high-density parallel computing on-chip.

The core of HOLO’s technology is algorithm–hardware co-design: dissecting the tensor-network algorithm at the software-logic level into computational units that can be hardware-implemented, then constructing a high-density, parallel, and scalable architecture with FPGA as the carrier.

HOLO analyzed tensor-network structures for quantum spin models such as the Heisenberg spin chain and the two-dimensional Ising model. These Hamiltonians decompose into local interaction terms that are encoded into local tensors; contracting tensor nodes corresponds to tensor products, matrix multiplications, and summation operations. Traditional CPUs run these tasks sequentially; GPUs provide broad parallelism but remain constrained by memory latency and kernel scheduling. FPGA architecture allows direct hardware definition of the required computational logic, eliminating redundant scheduling and enabling continuous pipelined data flow through on-chip high-speed caches.

HOLO implemented a Hierarchical Tensor Contraction Pipeline with three main levels:

• Input and scheduling layer: decomposes high-dimensional tensors into manageable blocks and performs data-flow scheduling and dependency analysis.
• Core computing layer: composed of multiple MAC arrays supporting tensor-contraction operations of arbitrary dimensions; each computing unit uses customized logic for pipelined parallel floating-point add/multiply operations.
• Output and reduction layer: merges, normalizes, and caches intermediate tensor states to provide inputs for subsequent iterations.

Using a combination of Verilog and high-level synthesis (HLS) tools, HOLO automatically generated tensor-operation circuits and adopted multi-partition strategies for different tensor-connectivity graphs. Static scheduling and data-reuse mechanisms enable the computing units to form a high-density on-chip parallel array, maximizing throughput under limited logic resources.

With FPGA as the core platform, HOLO’s parallelized hardware architecture accelerates quantum tensor-network computations. Through algorithm-structure reconstruction, logic-circuit mapping, pipelined design, and mixed-precision optimization, the company transformed complex tensor-network tasks into efficient FPGA logic operations, achieving performance roughly 1.7× faster than CPU implementations and improving energy efficiency by more than 2×. The result demonstrates FPGA’s potential for quantum simulation and supports practical hardware implementation of quantum algorithms and reconfigurable quantum-accelerator design.

Looking ahead, HOLO will continue its algorithm-to-circuit design philosophy, extending hardware implementation to more quantum computing core modules, including variational quantum eigensolvers (VQE), quantum linear system solvers (QLSA), and FPGA-based quantum machine-learning models, to build a comprehensive quantum-algorithm acceleration ecosystem. Continued work in this direction aims to make FPGA an important bridge between quantum and classical computing and to support industrial development of quantum technologies.

About MicroCloud Hologram Inc.

MicroCloud Hologram Inc. (NASDAQ: HOLO) is focused on research, development, and application of holographic technology. Its services include holographic LiDAR solutions, LiDAR point-cloud algorithm architecture, holographic imaging solutions, holographic LiDAR sensor chip design, and holographic intelligent vehicle-vision technology for advanced driver-assistance systems (ADAS). The company also provides holographic digital-twin technology services and maintains proprietary holographic-digital-twin technology resource libraries that combine software, 3D capture, space-data-driven data science, and cloud algorithms.

MicroCloud Hologram Inc. is advancing developments in quantum computing and quantum holography, and has indicated plans for significant investments in frontier technologies including blockchain, quantum computing, quantum holography, artificial intelligence, and AR.

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SOURCE MicroCloud Hologram Inc.